SDR Interference Emulator (based on InterOP hardware)
Key facts:
- ADC: 250 MS/s, 14/16 bits
- DAC: 1700 MS/s, 16 bits
- Tuning range: WBX/UBX: 50-2200/10-6000 MHz
- FPGA: ZYNQ Ultrascale+
- FPGA type: XCTU3CG-XCZU15EG
- Processor: Quad-core ARM® Cortex™-A53, MPCore™ up to 1.5GHz, Dual-core ARM Cortex-R5, MPCore™ up to 600MHz
Documentation:
- Datasheet
- Overview
- Getting started
- USB live image with operating system and SDR Interference Emulator software
- RFID interference demo
- Schematics
- FPGA documentation
- FPGA source code
- OS Petalinux source code
- Software source code
- Other source code
- Boot loader for firmware update of the Zynq family
- Reports